The present invention relates to methods and systems for data rate detection for multi-speed embedded clock serial receivers.
The past few years have seen a dramatic increase in the speed of data transmission capabilities among and between the various components of a computer system or between multiple computer systems connected together in a network configuration. Indeed, since the general acceptance of personal computer systems, data transmission speeds have grown with an almost power law dependence; about 1 MHz in the ""60""s, 10 MHz in the ""70""s, 100 MHz in the ""80""s, and 1 GHz speeds being routinely achieved in the ""90""s.
The development of optical fiber for transmission of digital data streams has become a particular enabling technology for modern day 1 GHz data transmission speeds and, in the computer industry, has given rise to a data transfer protocol and interface system termed Fibre-Channel. Fibre-Channel technology involves coupling various computer systems together with optical fiber or an electrically conductive (copper) cable and allows extremely rapid data transmission speeds between machines separated by potentially great distances. However, because of the physical characteristics of these types of systems, data is typically transmitted in a serial-fashion. In contrast, computer systems are configured to almost universally handle data in parallel fashion on byte-multiple signal busses (8-bit, 16-bit or 32-bit busses), making it incumbent on any data transmission system to provide some means for converting a 1 GHz serial data stream into a byte or byte-multiple parallel data stream. Conversely, since the fibre channel protocol contemplates two-way data transmission, computer systems that typically operate with parallel data structures must have some means for serializing a byte or byte-multiple data stream into a 1 GHz data signal suitable for transmission down an optical fiber or an electrically conductive (copper) cable.
Parallel data being serialized for high speed transmission is typically synchronous, in that the sequence of 1""s and 0""s making up the resulting serial data stream occurs with reference to a synchronized, uniform, single-frequency serializer clock signal. Encoding and transmitting the clock signal, together with data, would necessarily require an inordinate amount of valuable serial bandwidth, require an extra line to carry the clock, and reduce the overall data transmission speed of a fibre channel system because of clock skew issues. Even though individual bit level self-clocking is inherent in the serial data stream, some method of evaluating the data stream must be used in order that a transceiver or serial-to-parallel data recovery system may determine how to appropriately frame the binary data stream into bytes.
In accordance with the Fibre-Channel 10-bit Interface specification, amplified in ANSI X3.230-1994 document, an encoded byte is 10-bits in length and is referred to as a transmission character. Data provided over a typical computer system""s parallel architecture must be encoded and framed such that each data byte (8-bits from the point of view of the computer system) is formed into a transmission character, often termed a Fibre Channel 8B/10B encoded character. The resulting 8B/10B character must then be transmitted as 10 sequential bits at a 1.06 GHz data rate in accordance with the interface specification. Likewise, an incoming 8B/10B encoded transmission character must be received at a 1.06 GHz data rate and converted (framed) into the encoded 10 bit byte.
In the receiver case, many systems perform this function by using various types of clock recovery circuits, the most common of which is a phase-lock loop, which generates or regenerates a synchronous timing reference signal from a serial data stream and provides the timing reference to a data synchronizer or deserializer in order to mark-in time, the anticipated occurrence of a serial data bit. In effect, a phase-lock loop generates a synchronous stream of successive timing references, each timing reference representing, for example, a bit cell with which a data bit may be associated. For example, 10 consecutive timing references might represent a framed 8B/10B Fibre Channel transmission character which might then be latched out onto a 10-bit parallel bus by, for example, a deserializer comprising a 10-bit counter. Hence, a clock recovery circuit is an essential component in modem day GHz transceiver systems.
In like fashion, transmitter sections are configured to receive an 8B/10B encoded transmission character and convert the 10-bit byte into serial data and transmit the serialized data at a 1.06 GHz data rate.
The frequency of clock signals recovered by, for example, a receiver phase lock loop, is subject to a number of variations introduced by the electronic components of such systems, including transmission media effects. Typically, the electronic components in the data path introduce some elements of phase and frequency noise which are random in nature and, more particularly, have dramatically varying band width characteristics depending on the geometric and electronic variations in modem semiconductor manufacturing process parameters. A phase lock loop such as comprises a 1.06 GHz to 106 MHZ transceiver, must take these variations into account when attempting to deal with a 1.06 GHz serial data stream.
Implementations of such a transceiver, typically include at least a phase-locked loop (PLL) normally comprising a phase or phase and frequency detector, a charge pump, an analog filter, and some means for generating a synchronous clock signal, such as a voltage controlled oscillator (VCO).
During initialization, or power-on reset, during what is conventionally termed a frequency or velocity lock, the oscillation frequency of the VCO is determined by, and locked to, the frequency of an external clock provided for such purpose, just prior to receiving an incoming serial data stream. Once frequency or velocity lock is established, the VCO runs in what might be termed a quasi-flywheel mode at a mean frequency determined during velocity lock. Subsequent correction control to the VCO frequency is developed by phase-locking a transition edge of the synchronous VCO signal to a transition edge of the data ONE bits of an incoming serial data signal. Typically, both rising and falling edges can be used to make phase comparisons. The VCO is phase-locked to the incoming serial data stream by comparing the phase of the rising edge of the VCO clock signal to the phase of the rising edge of a data ONE bit, in a phase detector. Phase or time differences detected between the two rising edges causes a control signal to be issued to a charge pump which either pumps-up or pumps-down the VCO, thus directing the VCO to either speed up or slow down in response to frequency variation in the data stream.
An analog low pass filter is typically provided between the charge pump and the VCO to reject corrections resulting from random high-frequency variations of individual data bytes, and allow ideally only corrections resulting from consistent frequency shifts of the data stream. The filter is also used to provide for loop stability. The VCO is therefore locked to the mean phase of the data stream rather than to the phase of a particular data bit. Once phase-locked, the synchronous VCO signal provides for a recovered clock signal whose rate (frequency) is equal to the data bit rate or an integral multiple thereof.
Some receivers are capable of receiving data at multiple bit rates. Typically, the rates are even multiples of one another, e.g. factors of 2. The receiver must be able to determine the bit rate or data rate, lock a local clock to the data and perform word alignment. Data streams typically possess timing jitter and frequency variations that behave in an asynchronous and/or random manner. Data of one bit rate will often appear as legitimate data at another rate. These two factors can combine to make speed detection very difficult. Consider, for example, a bit pattern of 00110011. This bit pattern, when considered from the point of view of a higher bit rate, can be identical to the bit pattern 0101 at a lower rate.
Thus, a problem exists not being able to easily and automatically detect two or more different data rates in a robust manner. While attempts have been made in the past, they fall short of the mark of providing an automatic robust method. For example, one past system will typically assume that data is being received at a certain rate, e.g. the higher of two rates. The system will then analyze the data at the assumed rate to see if it can be successfully interpreted and follows the higher levels of transmission protocol. If the data does not make sense at the higher rate, then the lower rate will be used to analyze the data. This approach can be inefficient, especially in loop architectures where several nodes in a daisy chain sequentially detect their input data rate.
Accordingly, this invention arose out of concerns associated with providing improved methods and systems for data rate detection for multi-speed embedded clock serial receivers.
Methods and systems for data rate detection for multi-speed embedded clock serial receivers are described.
In one embodiment, a method of determining a data rate of a high speed serially transmitted data stream comprises statistically examining edge timing characteristics of the incoming data stream. Based on the edge characteristics, a signature is identified that is associated with the edge characteristics. Based on the identified signature, a data rate at which the data stream is being transmitted is determined.
In another embodiment, a method of determining a data rate of a high speed serially transmitted data stream comprises providing a clock signal at a first data rate. The clock signal has clock edges that are locked to data transitions of an incoming data stream. The method discriminates between data transitions that occur on odd and even clock edges and determines whether the data transitions occur, on average, on only one of odd or even clock edges, or whether the data transitions occur, on average, on both odd and even clock edges. Based on where the data transitions occur, the method ascertains a data rate of the incoming data.
In yet another embodiment, a clock extraction/data recovery circuit is provided for recovering an embedded clock and data from a high speed serially transmitted data stream. The circuit comprises a phase comparator that is configured to receive a high speed serially transmitted data stream and output indicia whenever the data stream experiences a data transition. A voltage controlled oscillator (VCO) is connected with the phase comparator and provides a clock signal having clock edges. The clock signal is locked to the data stream. A data rate detection circuit is connected with the phase comparator and receives the indicia that are output by the phase comparator. Based on the received indicia, the data rate detection circuit ascertains a data rate at which the data stream is transmitted.